The invention relates to a circuit arrangement for a quartz-controlled electrical clock comprising an oscillator stage, frequency divider stages, output stages and a stepping switch motor.
The circuits for quartz-controlled clocks, which have become known up to the present, having frequency dividers and stepping switch motors as the hand drive, have the important disadvantage of an undully long starting time.
To set the clock, the supply voltage is disconnected from the oscillator and from the frequency divider. Then the hands or the numerical indicators are set to the desired clock time. In order to restart the clock thereafter the supply voltage is applied to the integrated circuit built into the clock via the switch connected to the setting crown. This integrated circuit contains the oscillator, the frequency divider and the necessary output stages and is as a rule constructed with MIS field effect transistors. These transistors have a control electrode separated from the channel region by an insulating layer.
Up to the start of the second hand or the second numeral indicator, there results after the closure of the switch, still further delay times necessitated by the circuit design concept:
A. BUILD-UP PERIOD OF THE OSCILLATOR: ACCORDING TO THE OPERATING VOLTAGE UP TO 1 SEC.
B. TIME PERIOD UP TO THE APPEARANCE OF THE FIRST PULSE AT THE OUTPUT STAGES WHICH PULSE DRIVES THE MOTOR IN THE CORRECT DIRECTION IN ACCORDANCE WITH THE FINAL POSITION OF THE MOTOR ON DISCONNECTION OF THE CLOCK: MAXIMALLY 2 SEC.
For clocks which must not be incorrect in the course of a year by more than a few seconds, a setting accuracy of 2 to 3 seconds is not serviceable.